1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an array substrate for an LCD device having an improved contact property.
2. Discussion of the Related Art
LCD devices are developed as next generation display devices because of their lightweight, thin profile, and low power consumption characteristics. In general, an LCD device is a non-emissive display device that displays images using a refractive index difference having optical anisotropy properties of liquid crystal material that is interposed between a thin film transistor (TFT) array substrate and a color filter (C/F) substrate. Presently, among the various type of LCD devices commonly used, active matrix LCD (AM-LCD) devices have been developed because of their high resolution and superiority in displaying moving images. The AM-LCD device includes a TFT per each pixel region as a switching device, a first electrode for ON/OFF, and a second electrode used for a common electrode.
LCD devices can obtain a higher reliability and a stronger competitive power in price by selecting a metal of low resistivity and a strong corrosion resistance as a material for a metal line delivering a signal. Aluminum (Al) or Al alloy is widely used as the material for the metal line. However, as LCD devices become larger and a resolution of LCD devices becomes higher such as SVGA (Super Video Graphics Adapter), XGA (Extended Graphics Adapter), SXGA (Super Extended Graphics Adapter) and UXGA (Ultra Extended Graphics Adapter), a scanning time becomes shorter and a signal-treating speed becomes higher. To satisfy these needs, a metallic material of low resistance is selected as the material for the metal line. Accordingly, copper (Cu), which has a lower resistivity and a higher resistance to electromigration property than a conventional material is suggested for the metal line. However, since Cu has a poor adhesion to a glass substrate and a high diffusivity into a silicon material (e.g., insulating layer or semiconductor layer) under a relatively low temperature (about 200° C.), Cu cannot be used as the single material for the metal line.
To solve these problems, when a Cu line is selected as gate and data lines for an LCD device, a structure is suggested where an additional barrier layer is interposed between the glass substrate and the gate line, and between the semiconductor layer and the data line. The barrier layer improves an adhesion of the Cu line to the glass substrate and prevents a diffusion of Cu into the semiconductor layer. LCD devices having an improved aperture ratio and an improved display quality are briskly researched and developed by applying a Cu line including a barrier layer to an LCD device having an organic insulating layer of a low dielectric constant. For example, titanium (Ti) is used as a metallic material for the barrier layer.
In FIG. 1, a gate line 62 and a data line 74 cross each other and a thin film transistor (TFT) “T” is disposed at a crossing of the gate and data lines 62 and 74. A pixel region is defined by the gate and data lines 62 and 74 and a pixel electrode 88 at the pixel region is connected to the TFT “T.” Here, the pixel electrode 88 partially overlaps the gate and data lines 62 and 74. A passivation layer (not shown) of a low dielectric constant is interposed between the pixel electrode 88 and the data line 74 to prevent an electric interference therebetween. A gate pad 64 and a data pad 73 are disposed at one end of the gate line 62 and the data line 73, respectively. A gate pad terminal 90 and a data pad terminal 92 of the same material as the pixel electrode 88 are formed on the gate pad 64 and a data pad 73, respectively. Indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is mainly used as the material for the pixel electrode 88, the gate and data pad terminals 90 and 92. The gate and data lines 62 and 74 have a double-layered structure of an upper intrinsic copper layer and a lower barrier layer such as Cu/Ti. Each copper layer including the barrier layer of the TFT “T” and the gate and data pads 64 and 73 is connected to respective ITO electrode of the pixel electrode 88, the gate and data pad terminals 90 and 92 through respective a drain contact hole 80, and gate and data pad contact holes 82 and 84.
FIGS. 2A to 2D are schematic cross-sectional views, which are taken along a line II—II of FIG. 1, showing a fabricating process of an array substrate for an LCD device of a high aperture ratio using a Cu line including a barrier layer of the related art.
In FIG. 2A, first and second passivation layers 52 and 54 are formed over a TFT “T” and a gate pad 64. Here, a gate insulating layer 50, the first and second passivation layers 52 and 54 are sequentially formed on the gate pad 64. The TFT “T” includes a gate electrode 60, a semiconductor layer 70, source and drain electrodes 76 and 78. The gate insulating layer 50 and the first passivation layer 52 are made of silicon nitride (SiNx), and the second passivation layer 54 is made of an organic insulating material having a low dielectric constant. Generally, the gate insulating layer 50 and the first passivation layer 52 are formed by using a deposition apparatus such as a chemical vapor deposition (CVD) apparatus, and the second passivation layer 54 is formed by using a coating apparatus such as a spinner.
FIG. 2B, first and second open holes 80a and 82b respectively corresponding to the gate pad 64 and the drain electrode 78 are formed in the second passivation layer 54. For example, when the second passivation layer 54 is made of a photosensitive organic insulating material, the first and second open holes 80a and 82b are formed through a photolithography process including an exposure, a development and a curing.
In FIG. 2C, a gate pad contact hole 80 exposing the gate pad 64 and a drain contact hole 82 exposing the drain electrode 78 are formed through dry-etching a insulating material corresponding to the first and second open holes 80a and 82b (of FIG. 2B). In detail, the gate pad contact hole 80 is formed through the first and second passivation layers 52 and 54, and a gate insulating layer 50, and the drain contact hole 82 is formed through the first and second passivation layers 52 and 54. Here, after a substrate having the first and second open holes 80a and 82b is loaded in a vacuum chamber and a reaction gas such as SH6 and CH4 (methane) is injected into the vacuum chamber, plasma is generated in the vacuum chamber under a specific pressure. Thus, the insulating material corresponding to the first and second open holes 80a and 82b (of FIG. 2B) is etched through a bombardment or a chemical reaction between the ionized reaction gas and a thin film of the insulating material.
In FIG. 2D, a gate pad terminal 90 and a pixel electrode 88 of a transparent conductive material are formed on the second passivation layer 54. The gate pad terminal 90 is connected to the gate pad 64 through the gate pad contact hole 80, and the pixel electrode 88 is connected to the drain electrode 78 through the drain contact hole 82.
FIG. 3 is a schematic cross-sectional view showing an inferior contact hole of an array substrate for an LCD device of a high aperture ratio using a Cu line including a barrier layer of the related art.
In FIG. 3, a metal line 10 includes a first metal layer 10a as a barrier layer and a second metal layer 10b of a Cu layer on the first layer 10a. A first passivation layer 12 of silicon insulating material and a second passivation layer 14 of an organic insulating material are sequentially formed on the metal line 10. The first and second passivation layers 12 and 14 have a contact hole 16 exposing the metal line 10. During a dry-etching process for the contact hole 16 in the first and second passivation layers 12 and 14, an organic material of the second passivation layer 14 loses its moisture due to a reaction with plasma to be an organic residue 15 on the second metal layer 10b. The organic residue 15 is seldom eliminated through a following cleaning process and causes a inferior contact property between an ITO layer and the Cu layer during a forming process of pad terminals and a pixel electrode of ITO. As a result, the organic residue 15 interferes an electric connection between the ITO layer and the Cu layer to cause an inferiority of electric signal input.